ii
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
Document DB14-000104-00, First Edition (June 2001)
This document describes Rev 0A of the LSI Logic Corporation ARM946E-S and
will remain the official reference source for all revisions/releases of this product
until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, CoreWare, and Right-First-Time are registered
trademarks or trademarks of LSI Logic Corporation. ARM is a registered
trademark of ARM Limited, used under license. All other brand and product
names may be trademarks of their respective companies.
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ARM946E-S Microprocessor Core with Cache Technical Manual
iii
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and Technical Reference Manual for
the ARM946E-S. It contains a complete functional description for the
product and includes complete physical and electrical specifications for
this product.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
Engineers and managers who are evaluating the processor for
possible use in a system
Engineers who are designing the processor into a system
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, provides an introduction to the ARM946E-S.
Chapter 2, Signal Descriptions
, describes the signals used in the
ARM946E-S.
Chapter 3, Programmer's Model
, describes the programmer's model of
the ARM946E-S and includes a summary of the ARM946E-S
coprocessor registers.
Chapter 4, Caches
, describes the ARM946E-S cache implementation.
Chapter 5, Protection Unit
, describes the ARM946E-S protection unit.
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Preface
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
Chapter 6, Tightly Coupled SRAM
, describes the requirements and
operation of the tightly coupled SRAM.
Chapter 7, Bus Interface Unit and Write Buffer
, describes the
operation of the Bus Interface Unit and write buffer.
Chapter 8, External Coprocessor Interface
, describes the coprocessor
interface and the operation of common coprocessor instructions.
Chapter 9, Debug Interface
, describes the debug support for the
ARM946E-S and the EmbeddedICE-RT logic.
Chapter 10, ETM Interface
, describes the ETM interface, including
details of how to enable the interface.
Chapter 11, Test Support
, describes the test methodology used for the
ARM946E-S synthesized logic and tightly coupled SRAM.
Appendix A, AC Parameters
, describes the timing parameters applicable
to the ARM946E-S.
Related Publications
ARM Architecture Reference Manual available from ARM Ltd. as
document No. ARM DDI 0100.
ARM9E-S Technical Reference Manual available from ARM Ltd. as
document No.ARM DDI 0165.
AMBA Specification (Rev 2.0) available from ARM Ltd. as document No.
ARM IHI 0011.
Embedded Trace Macrocell Specification (Rev 1.0) available from ARM
Ltd. as document number IHI 0014E.
Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
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